What does "net" stand for in Verilog?

I'm just starting to learn Verilog. As I understand, Verilog has net datatypes. What does net stand for?

asked Apr 2, 2012 at 11:16 Randomblue Randomblue 115k 148 148 gold badges 361 361 silver badges 554 554 bronze badges

4 Answers 4

A net is such a data type, where you don't use it for storing values. They represent physical connections. You can think of wire as a net data type.
You can see more on nets here.

answered Apr 2, 2012 at 11:25 2,262 22 22 silver badges 30 30 bronze badges

A wire is not a datatype,; it is one of a few categories of nets.Net's represent connections as opposed to variables which hold values.

Commented Nov 8, 2020 at 17:24

A net is short for network, and a network is a group of devices that share a common connection, a wire in most cases here. Net's represent connections as opposed to variables which hold values. I wrote a short article to explain why Verilog has nets.

answered Sep 14, 2013 at 16:03 41.8k 3 3 gold badges 25 25 silver badges 64 64 bronze badges

Nets : represent structural connections between components.Nets have values continuously driven on them by the outputs of the devices to which they are connected to. i.e. nets get the output value of their drivers. If a net has no driver, it gets the value of z(high impedance).

answered Jun 16, 2015 at 6:09 prasad pattadakal prasad pattadakal 11 3 3 bronze badges

Could you please elaborate more your answer adding a little more description about the solution you provide?

Commented Jun 16, 2015 at 6:35

IEEE 1364-2005

4.2 Nets and variables:

There are two main groups of data types: the variable data types and the net data types. These two groups differ in the way that they are assigned and hold values. They also represent different hardware structures.

4.2.1 Net declarations:

The net data types can represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate.

and the syntax table that follows says:

net_type ::= supply0 | supply1 | tri | triand | trior | tri0 | tri1 | uwire | wire | wand | wor

Interpretation

A net is a set of data types, one of which is wire .

Those data-types have in common that unlike registers they don't have memory: they are just intermediate results determined by their input. Much like the intuitive notion of wires.